Author: Xianlong Hong    
Paper Titile Authors Year
Rethinking thermal via planning with timing-power-temperature dependence for 3D Ics Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong: 2011
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong 2010
Simultaneous slack budgeting and retiming for synchronous circuits optimization Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang 2010
A novel thermal optimization flow using incremental floorplanning for 3D ICs Xin Li, Yuchun Ma, Xianlong Hong 2009
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong 2009
LP based white space redistribution for thermal via planning and performance optimization in 3D Ics Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong 2008
Vertical via design techniques for multi-layered P/G networks Shuai Li, Jin Shi, Yici Cai, Xianlong Hong 2008
Symmetry constraint based on mismatch analysis for analog layout in SOI technology Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto 2008
Heuristic power/ground network and floorplan co-design method Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong 2008
Low power clock buffer planning methodology in F-D placement for large scale circuit design Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian 2008
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong 2007
Logic and Layout Aware Voltage Island Generation for Low Power Design Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong 2007
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan 2007
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong 2007
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 2007
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang 2007
DraXRouter: global routing in X-Architecture with dynamic resource assignment Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan 2006
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong 2006
Signal-path driven partition and placement for analog circuit Di Long, Xianlong Hong, Sheqin Dong 2006
Efficient early stage resonance estimation techniques for C4 package Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong 2006
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong 2006
Relaxed hierarchical power/ground grid analysis Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu 2005
VLSI on-chip power/ground network optimization considering decap leakage currents Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan 2005
An-OARSMan: obstacle-avoiding routing tree construction with good length performance Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan 2005
Clock network minimization methodology based on incremental placement Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu 2005
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He 2005
Register placement for low power clock network Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu 2005
An improved P-admissible floorplan representation based on Corner Block List Renshen Wang, Sheqin Dong, Xianlong Hong 2005
The polygonal contraction heuristic for rectilinear Steiner tree construction Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan 2005
LFF algorithm for heterogeneous FPGA floorplanning Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu 2005
Analysis of buffered hybrid structured clock networks Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan 2005
A buffer planning algorithm with congestion optimization Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: 2004
Buffer allocation algorithm with consideration of routing congestion Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu 2004
Efficient octilinear Steiner tree construction based on spanning graphs Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang 2004
A buffer planning algorithm based on dead space redistribution Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2003
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu 2003
A path-based timing-driven quadratic placement algorithm Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai 2003
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu 2003
Congestion driven incremental placement algorithm for standard cell layout Zhuoyuan Li, Weimin Wu, Xianlong Hong 2003
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction Taotao Lu, Zeyi Wang, Xianlong Hong 2003
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu 2003
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI Shuzhou Fang, Zeyi Wang, Xianlong Hong 2002
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu 2002
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2002
VLSI block placement using less flexibility first principles Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu 2001
A new congestion-driven placement algorithm based on cell inflation Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao 2001
VLSI floorplanning with boundary constraints based on corner block list Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2001
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong 2000
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method Jiangchun Gu, Zeyi Wang, Xianlong Hong 2000
Area routing oriented hierarchical corner stitching with partial bin Zhang Yan, Baohua Wang, Yici Cai, Xianlong Hong 2000
MMP: a novel placement algorithm for combined macro block and standard cell layout design Hong Yu, Xianlong Hong, Yici Cai 2000
A New Global Routing Algorithm Independent Of Net Ordering Haiyun Bao, Xianlong Hong, Yici Cai 1999
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong 1999
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance Jinsong Hou, Zeyi Wang, Xianlong Hong 1999
A Timing-Driven Block Placer Based on Sequence Pair Model Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai 1999
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells Xiaohai Wu, Changge Qiao, Xianlong Hong 1999
VEAP: Global optimization based efficient algorithm for VLSI placement Tianming Kong, Xianlong Hong, Changge Qiao 1997
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