Author: Yici Cai    
Paper Titile Authors Year
HLIFT: A high-level information flow tracking method for detecting hardware Trojans Chenguang Wang, Yici Cai, Qiang Zhou 2018
ASAX: Automatic security assertion extraction for detecting Hardware Trojans Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang 2018
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu 2018
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai 2017
Sequence-pair-based placement and routing for flow-based microfluidic biochips Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai 2016
Early stage real-time SoC power estimation using RTL instrumentation Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai 2015
VFGR: A very fast parallel global router with accurate congestion modeling Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen 2014
Time-domain performance bound analysis for analog and interconnect circuits considering process variations Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang 2014
Fast vectorless power grid verification using maximum voltage drop location estimation Wei Zhao, Yici Cai, Jianlei Yang 2014
Performance bound and yield analysis for analog circuits under process variations Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, YiciCai 2013
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification Wei Zhao, Yici Cai, Jianlei Yang 2013
Thermal-aware power network design for IR drop reduction in 3D ICs Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie 2012
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits Hailong Yao, Yici Cai, Qiang Gao 2012
Efficient power grid integrity analysis using on-the-fly error check and reduction Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai 2010
Efficient model reduction of interconnects via double gramians approximation Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai 2010
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong 2009
Vertical via design techniques for multi-layered P/G networks Shuai Li, Jin Shi, Yici Cai, Xianlong Hong 2008
Heuristic power/ground network and floorplan co-design method Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong 2008
Low power clock buffer planning methodology in F-D placement for large scale circuit design Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian 2008
Logic and Layout Aware Voltage Island Generation for Low Power Design Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong 2007
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan 2007
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang 2007
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong 2006
Efficient early stage resonance estimation techniques for C4 package Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong 2006
Relaxed hierarchical power/ground grid analysis Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu 2005
VLSI on-chip power/ground network optimization considering decap leakage currents Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan 2005
Clock network minimization methodology based on incremental placement Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu 2005
Register placement for low power clock network Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu 2005
Analysis of buffered hybrid structured clock networks Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan 2005
A buffer planning algorithm with congestion optimization Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan 2004
Buffer allocation algorithm with consideration of routing congestion Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A buffer planning algorithm based on dead space redistribution Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2003
A path-based timing-driven quadratic placement algorithm Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai 2003
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu 2003
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu 2003
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2002
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu 2002
A new congestion-driven placement algorithm based on cell inflation Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao 2001
VLSI floorplanning with boundary constraints based on corner block list Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2001
Area routing oriented hierarchical corner stitching with partial bin Zhang Yan, Baohua Wang, Yici Cai, Xianlong Hong 2000
MMP: a novel placement algorithm for combined macro block and standard cell layout design Hong Yu, Xianlong Hong, Yici Cai 2000
A New Global Routing Algorithm Independent Of Net Ordering Haiyun Bao, Xianlong Hong, Yici Cai 1999
A Timing-Driven Block Placer Based on Sequence Pair Model Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai 1999