Author: Jason Cong    
Paper Titile Authors Year
FPGA-based accelerator for long short-term memory recurrent neural networks Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong 2017
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong 2017
A scalable communication-aware compilation flow for programmable accelerators Jason Cong, Hui Huang, Mohammad Ali Ghodrat 2016
Optimizing routability in large-scale mixed-size placement Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao 2013
Platform characterization for Domain-Specific Computing. Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou 2012
Compilation and architecture support for customized vector instruction extension Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza 2012
An integrated and automated memory optimization flow for FPGA behavioral synthesis Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong 2012
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong 2011
On the futility of statistical power optimization Jason Cong, Puneet Gupta, John Lee 2009
A multilevel analytical placement for 3D ICs Jason Cong, Guojie Luo 2009
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang 2008
Scheduling with integer time budgeting for low-power optimization Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong 2008
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong 2008
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang 2007
Thermal-Aware 3D IC Placement Via Transformation Jason Cong, Guojie Luo, Jie Wei, Yan Zhang 2007
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 2007
An automated design flow for 3D microarchitecture evaluation Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang 2006
A robust detailed placement for mixed-size IC designs Jason Cong, Min Xie 2006
Optimal module and voltage assignment for low-power Deming Chen, Jason Cong, Junjuan Xu 2005
Bitwidth-aware scheduling and binding in high-level synthesis Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng 2005
Are we ready for system-level synthesis? Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe 2005
Fast floorplanning by look-ahead enabled recursive bipartitioning Jason Cong, Michail Romesis, Joseph R. Shinnerl 2005
Thermal-driven multilevel routing for 3-D ICs. Jason Cong, Yan Zhang 2005
Microarchitecture evaluation with floorplanning and interconnect pipelining Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong 2005
Register binding and port assignment for multiplexer optimization Deming Chen, Jason Cong 2004
Optimality and scalability study of existing placement algorithms Chin-Chih Chang, Jason Cong, Min Xie 2003
Multi-level placement for large-scale mixed-size IC designs Chin-Chih Chang, Jason Cong, Xin Yuan 2003
Improved crosstalk modeling for noise constrained interconnect optimization Jason Cong, David Zhigang Pan, Prasanna V. Srinivas 2001
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu 2000
Edge separability based circuit clustering with application to circuit partitioning Jason Cong, Sung Kyu Lim 2000
Performance driven multiway partitioning Jason Cong, Sung Kyu Lim 2000
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs Jason Cong, Songjie Xu 2000
Multi-way partitioning using bi-partition heuristics Maogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh 2000
Relaxed Simulated Tempering for VLSI Floorplan Designs Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong 1999
Interconnect Delay Estimation Models for Synthesis and Design Planning Jason Cong, David Zhigang Pan 1999
Exploitation signal flow and logic dependency in standard cell placement Jason Cong, Dongmin Xu 1995
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