Author: Chung-Kuan Cheng    
Paper Titile Authors Year
SP&R: Simultaneous Placement and Routing Framework for Standard Cell Synthesis in Sub-7nm Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng 2020
Layer minimization in escape routing for staggered-pin-array PCBs Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng 2013
Character design and stamp algorithms for Character Projection Electron-Beam Lithography Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham 2012
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng 2010
On-chip power network optimization with decoupling capacitors and controlled-ESRs Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng 2010
Parallel transistor level circuit simulation using domain decomposition methods He Peng, Chung-Kuan Cheng 2009
High performance on-chip differential signaling using passive compensation for global communication Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng 2009
Noise minimization during power-up stage for a multi-domain power network Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng 2009
High performance current-mode differential logic Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto 2008
Timing-power optimization for mixed-radix Ling adders by integer linear programming Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng 2008
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis 2007
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen 2007
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris 2007
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton 2006
An unconditional stable general operator splitting method for transistor level transient analysis Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh 2006
A multi-level transmission line network approach for multi-giga hertz clock distribution Hongyu Chen, Chung-Kuan Cheng 2005
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen 2005
Integrated algorithmic logical and physical design of integer multiplier Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng 2005
Constructing zero-deficiency parallel prefix adder of minimum depth Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham 2005
Efficient transient simulation for transistor-level analysis Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh 2005
Optimal planning for mesh-based power distribution Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang 2004
A buffer planning algorithm with congestion optimization Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
Buffer allocation algorithm with consideration of routing congestion Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A multiple level network approach for clock skew minimization with process variations Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng 2004
A buffer planning algorithm based on dead space redistribution Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2003
The Y-architecture: yet another on-chip interconnect solution Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng 2003
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu 2003
RCLK-VJ network reduction with Hurwitz polynomial approximation Zhanhai Qin, Chung-Kuan Cheng 2003
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2002
Toward better wireload models in the presence of obstacles Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt 2001
VLSI floorplanning with boundary constraints based on corner block list Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2001
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng 2000
A Performance-Driven I/O Pin Routing Algorithm Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen 1999
A building block placement tool Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng 1997
A new layout-driven timing model for incremental layout optimization Fang-Jou Liu, John Lillis, Chung-Kuan Cheng 1997
Performance driven multiple-source bus synthesis using buffer insertion Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin 1995