Author: Hidetoshi Onodera    
Paper Titile Authors Year
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi 2019
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera 2016
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations Islam A. K. M. Mahfuzul, Hidetoshi Onodera 2016
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera 2015
Microarchitectural-level statistical timing models for near-threshold circuit design Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera 2015
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera 2013
Dependable VLSI Platform using Robust Fabrics Hidetoshi Onodera 2013
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera 2012
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera 2011
Dependable VLSI: device, design and architecture: how should they cooperate? Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe 2009
Statistical gate delay model for Multiple Input Switching Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera 2008
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs Kazutoshi Kobayashi, Hidetoshi Onodera 2008
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera 2007
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera 2007
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera 2006
Interconnect RL extraction at a single representative frequency Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2006
Timing analysis considering temporal supply voltage fluctuation Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera 2005
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera 2005
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera 2005
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera 2005
Return path selection for loop RL extraction Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2005
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera 2004
Representative frequency for interconnect R(f)L(f)C extraction Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2004
An SoC architecture and its design methodology using unifunctional heterogeneous processor array Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera 2004
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera 2003
A statistical gate delay model for intra-chip and inter-chip variabilities Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera 2003
Post-layout transistor sizing for power reduction in cell-based design Masanori Hashimoto, Hidetoshi Onodera 2001
A vector-pipeline DSP for low-rate videophones Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera 2001
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori 2001
A dynamically phase adjusting PLL with a variable delay Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera 2001
A method for linking process-level variability to system performances Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru 2000
A functional memory type parallel processor for vector quantization Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru 1997
A current mode cyclic A/D converter with a 0.8 μm CMOS process Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru 1997
A model-adaptable MOSFET parameter extraction system Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru 1995