Author: Yu Wang    
Paper Title Authors Year
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators Hanbo Sun, Zhenhua Zhu, Yi Cai, Xiaoming Chen, Yu Wang, Huazhong Yang 2020
Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search Shulin Zeng, Hanbo Sun, Yu Xing, Xuefei Ning, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang 2020
FTT-NAS: Discovering Fault-Tolerant Neural Architecture Wenshuo Li, Xuefei Ning, Guangjun Ge, Xiaoming Chen, Yu Wang, Huazhong Yang 2020
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory Juejian Wu, Yixin Xu, Bowen Xue, Yu Wang, Yongpan Liu, Huazhong Yang, Xueqing Li 2020
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek 2019
Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator Jilan Lin, Zhenhua Zhu, Yu Wang, Yuan Xie 2019
Fault tolerance in neuromorphic computing systems Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty 2019
Training low bitwidth convolutional neural network on RRAM Yi Cai, Tianqi Tang, Lixue Xia, Ming Cheng, Zhenhua Zhu, Yu Wang, Huazhong Yang 2018
Computation-oriented fault-tolerance schemes for RRAM computing systems Wenqin Huangfu, Lixue Xia, Ming Cheng, Xiling Yin, Tianqi Tang, Boxun Li, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, Huazhong Yang 2017
Binary convolutional neural network on RRAM Tianqi Tang, Lixue Xia, Boxun Li, Yu Wang, Huazhong Yang 2017
Performance-centric register file design for GPUs using racetrack memory Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li 2016
Technological exploration of RRAM crossbar array for matrix-vector multiplication Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang 2015
Modeling and optimization of low power resonant clock mesh Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang 2015
An accurate and low-cost PM2.5 estimation method based on Artificial Neural Network Lixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang 2015
Statistical analysis of random telegraph noise in digital circuits Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang 2014
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design Miao Hu, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li 2014
Training itself: Mixed-signal training acceleration for memristor-based neural network Boxun Li, Yuzhi Wang, Yu Wang, Yiran Chen, Huazhong Yang 2014
HS3DPG: Hierarchical simulation for 3D P/G network Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang 2013
An adaptive LU factorization algorithm for parallel circuit simulation  Xiaoming Chen, Yu Wang, Huazhong Yang 2012
Thermal-aware power network design for IR drop reduction in 3D ICs Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie 2012
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs Jing Xie, Yu Wang, Yuan Xie 2012
On-chip hybrid power supply system for wireless sensor nodes Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang 2011
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong 2011
Network flow-based simultaneous retiming and slack budgeting for low power design Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto 2011
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach 2010
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach 2010
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 2010
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong 2010
Simultaneous slack budgeting and retiming for synchronous circuits optimization Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang 2010
A framework for estimating NBTI degradation of microarchitectural components Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan 2009
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang 2008
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