Author: Yao-Wen Chang    
Paper Title Authors Year
Unified Redistribution Layer Routing for 2.5D IC Packages Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang 2020
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo 2019
An effective legalization algorithm for mixed-cell-height standard cells Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan 2017
Circular-contour-based obstacle-aware macro placement Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang 2016
Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts Zhi-Wen Lin, Yao-Wen Chang 2016
Recent research development and new challenges in analog layout synthesis Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung 2016
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang 2015
Non-stitch triple patterning-aware routing based on conflict graph pre-coloring Po-Ya Hsu, Yao-Wen Chang 2015
Detailed-Routing-Driven analytical standard-cell placement Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang 2015
Layer minimization in escape routing for staggered-pin-array PCBs Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng 2013
Symmetrical buffered clock-tree synthesis with supply-voltage alignment Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao 2013
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 2010
TRECO: dynamic technology remapping for timing engineering change orders. Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang 2010
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang 2010
High-performance global routing with fast overflow reduction. Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang 2009
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang 2007
A novel framework for multilevel full-chip gridless routing. Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin 2006
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen 2006
Simultaneous block and I/O buffer floorplanning for flip-chip design Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang 2006
Multilevel full-chip gridless routing considering optical proximity correction. Tai-Chen Chen, Yao-Wen Chang 2005
Placement with symmetry constraints for analog layout design using TCG-S Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang 2005
SoC test scheduling using the B-tree based floorplanning technique. Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang 2005
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization Yi-Hui Cheng, Yao-Wen Chang 2004
Layout techniques for on-chip interconnect inductance reduction. Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang 2004
Temporal floorplanning using 3D-subTCG Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen 2004
Simultaneous floorplanning and buffer block planning Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao 2003
Noise-aware buffer planning for interconnect-driven floorplanning Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang 2003
Graph matching-based algorithms for array-based FPGA segmentation design and routing Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang 2003