Author: Masanori Hashimoto    
Paper Title Authors Year
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo 2020
Soft Error and Its Countermeasures in Terrestrial Environment Masanori Hashimoto, Wang Liao 2020
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits Yutaka Masuda, Masanori Hashimoto: 2018
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li 2016
An oscillator-based true random number generator with process and temperature tolerance Takehiko Amaki, Masanori Hashimoto, Takao Onoye 2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera 2015
Area efficient device-parameter estimation using sensitivity-configurable ring oscillator Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye 2015
Body bias clustering for low test-cost post-silicon tuning Shuta Kimura, Masanori Hashimoto, Takao Onoye 2012
Jitter amplifier for oscillator-based true random number generator Takehiko Amaki, Masanori Hashimoto, Takao Onoye 2011
Run-time adaptive performance compensation using on-chip sensors Masanori Hashimoto: 2011
Device-parameter estimation with on-chip variation sensors considering random variability Kenichi Shinkai, Masanori Hashimoto 2011
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye 2010
Gate delay estimation in STA under dynamic power supply noise Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto 2010
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye 2009
High performance on-chip differential signaling using passive compensation for global communication Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng 2009
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye 2008
High performance current-mode differential logic Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto 2008
Interconnect RL extraction at a single representative frequency Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2006
Timing analysis considering temporal supply voltage fluctuation Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera 2005
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera 2005
On-chip thermal gradient analysis and temperature flattening for SoC design Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto 2005
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera 2005
Return path selection for loop RL extraction Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2005
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera 2004
Representative frequency for interconnect R(f)L(f)C extraction. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera 2004
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera 2003
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto 2003
Post-layout transistor sizing for power reduction in cell-based design Masanori Hashimoto, Hidetoshi Onodera 2002
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