Author: Kaushik Roy    
Paper Title Authors Year
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses Abhronil Sengupta, Karthik Yogendra, Deliang Fan, Kaushik Roy 2016
Efficient embedded learning for IoT devices Swagath Venkataramani, Kaushik Roy, Anand Raghunathan 2016
Computing with coupled Spin Torque Nano Oscillators Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy 2016
"All Programmable SOC FPGA for networking and computing in big data infrastructure" Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider 2014
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy 2011
Improved clock-gating control scheme for transparent pipeline Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy 2010
Micro-scale energy harvesting: a system design perspective Chao Lu, Vijay Raghunathan, Kaushik Roy 2010
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy 2009
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy 2009
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations Mesut Meterelliyoz, Kaushik Roy 2009
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching Swaroop Ghosh, Kaushik Roy 2008
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy 2008
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy 2006
Speed binning aware design methodology to improve profit under parameter variations Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 2006
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy 2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh 2006
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor Yiran Chen, Kaushik Roy, Cheng-Kok Koh 2004
Adaptive supply voltage technique for low swing interconnects Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy 2004
Integer linear programming-based synthesis of skewed logic circuits Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 2003
Robust high-performance low-power carry select adder. Woopyo Jeong, Kaushik Roy 2003
A metric for analyzing effective on-chip inductive coupling. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 2003
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh 2002
Dynamic noise analysis with capacitive and inductive coupling Seung Hoon Choi, Bipul C Paul, Kaushik Roy 2002
Power Consumption in XOR-Based Circuits Yibin Ye, Kaushik Roy, Rolf Drechsler 1999
Efficient synthesis of AND/XOR networks Yibin Ye, Kaushik Roy 1997
Statistical estimation of combinational and sequential CMOS digital circuit activity considering uncertainty of gate delays Tan-Li Chou, Kaushik Roy 1997