Author: Sachin S. Sapatnekar    
Paper Title Authors Year
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatneka, Bangqi Xu 2020
SeFAct: selective feature activation and early classification for CNNs Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar 2019
Logic and memory design using spin-based circuits. Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar 2016
A retargetable and accurate methodology for logic-IP-internal electromigration assessment. Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella 2015
Predicting circuit aging using ring oscillators. Deepashree Sengupta, Sachin S. Sapatnekar 2014
Incremental power network analysis using backward random walks Baktash Boghrati, Sachin S. Sapatnekar 2012
The impact of hot carriers on timing in large circuits Jianxin Fang, Sachin S. Sapatnekar 2012
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation Saket Gupta, Sachin S. Sapatnekar 2012
BTI-aware design using variable latency units Saket Gupta, Sachin S. Sapatnekar 2012
Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. Jianxin Fang, Sachin S. Sapatnekar 2011
Incremental solution of power grids using random walks Baktash Boghrati, Sachin S. Sapatnekar 2010
Current source modeling in the presence of body bias Saket Gupta, Sachin S. Sapatnekar 2010
Physical design techniques for optimizing RTA-induced variations Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar 2010
Application-specific 3D Network-on-Chip design using simulated allocation Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar 2010
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar 2009
Addressing thermal and power delivery bottlenecks in 3D circuits Sachin S. Sapatnekar 2009
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar 2009
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar 2006
A fixed-die floorplanning algorithm using an analytical approach Yong Zhan, Yan Feng, Sachin S. Sapatnekar 2006
Electrothermal analysis and optimization techniques for nanoscale integrated circuits Yong Zhan, Brent Goplen, Sachin S. Sapatnekar 2006
Temperature-aware routing in 3D ICs Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar 2006
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up Yong Zhan, Sachin S. Sapatnekar 2005
Buffering global interconnects in structured ASIC design Tianpei Zhang, Sachin S. Sapatnekar 2005
Hierarchical random-walk algorithms for power grid analysis Haifeng Qian, Sachin S. Sapatnekar 2004
An efficient algorithm for low power pass transistor logic synthesis Rupesh S Shelar, Sachin S Sapatnekar 2002