Author: Sri Parameswaran    
Paper Titile Authors Year
WEID: Worst-Case Error Improvement in Approximate Dividers Hassaan Saadat, Haris Javaid Aleksandar Ignjatovic, Sri Parameswaran 2020
MESGA: An MPSoC based embedded system solution for short read genome alignment Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran 2018
CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support Florencia Irena, Daniel Murphy, Sri Parameswaran 2018
Improving tag generation for memory data authentication in embedded processor systems Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu 2016
Speeding up single pass simulation of PLRUt caches Josef Schneider, Jorgen Peddersen, Sri Parameswaran 2015
ADAPT: An adaptive manycore methodology for software pipelined applications Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran: 2015
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide 2014
A scorchingly fast FPGA-based Precise L1 LRU cache simulator Josef Schneider, Jorgen Peddersen, Sri Parameswaran 2014
Multi-mode pipelined MPSoCs for streaming applications Haris Javaid, Daniel Witono, Sri Parameswaran 2013
RExCache: Rapid exploration of unified last-level cache Su Myat Min, Haris Javaid, Sri Parameswaran 2013
HitME: low power Hit MEmory buffer for embedded systems Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic: 2009
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks Jeremy Chan, Sri Parameswaran 2008
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time Jorgen Peddersen, Sri Parameswaran 2007
A novel instruction scratchpad memory optimization method based on concomitance metric Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran 2006
Finding optimal L1 cache configuration for embedded systems Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran 2006
Battery-aware instruction generation for embedded processors Newton Cheung, Sri Parameswaran, Jörg Henkel 2005
Multi-parametric improvements for embedded systems using code-placement and address bus coding Sri Parameswaran, Jörg Henkel, Haris Lekatsas 2003
SWASAD: An ASIC Design for High Speed DNA Sequence Matching Tony Han, Sri Parameswaran 2002
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation Allan Rae, Sri Parameswaran 2000
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines Hui Guo, Sri Parameswaran 1998
HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial) Sri Parameswaran 1998
Power Reduction in Pipelines Sri Parameswaran, Hui Guo 1998
Power consumption in CMOS combinational logic blocks at high frequencies Sri Parameswaran, Hui Guo 1997
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Reclocking for high-level synthesis
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran 1995