Author: Nozomu Togawa    
Paper Titile Authors Year
Theory of Ising Machines and a Common Software Platform for Ising Machines Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa 2020
FPGA-based Heterogeneous Solver for Three-Dimensional Routing Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa 2020
A bit-write reduction method based on error-correcting codes for non-volatile memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa 2015
Scan-based attack against elliptic curve cryptosystems Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2010
Exact and fast L1 cache simulation for embedded systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2009
GECOM: Test data compression combined with all unknown response masking Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2008
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n) Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2008
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2006
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki 2006
Reconfigurable adaptive FEC system with interleaving Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto 2005
A processor core synthesis system in IP-based SoC design Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2005
A cosynthesis algorithm for application specific processors with heterogeneous datapaths Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2004
Instruction set and functional unit synthesis for SIMD processor cores Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki 2004
A thread partitioning algorithm in low power high-level synthesis Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2004
A hardware/software partitioning algorithm for SIMD processor cores Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki 2003
VLSI Architecture for a Flexible Motion Estimation with Parameters Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2002
Area/delay estimation for digital signal processor cores Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki 2001
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper) Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki 2000
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki 1999
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki 1998
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki 1998
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki 1997
返回
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki 1995