Author: Jing-Yang Jou    
Paper Titile Authors Year
Chain-based pin count minimization for general-purpose digital microfluidic biochips Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou 2016
A read-write aware DRAM scheduling for power reduction in multi-core systems Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou 2014
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou 2013
Thread affinity mapping for irregular data access on shared Cache GPGPU Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou 2012
Equivalence checking of scheduling with speculative code transformations in high-level synthesis Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou 2011
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou 2007
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou 2006
FSM-based transaction-level functional coverage for interface compliance verification Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou 2006
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou 2005
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou 2005
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou 2004
On compliance test of on-chip bus for SOC Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou 2004
Layout techniques for on-chip interconnect inductance reduction Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang 2004
An efficient IP-level power model for complex digital circuits Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou 2003
Simultaneous floorplanning and buffer block planning Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao 2003
An automatic interconnection rectification technique for SoC design integration Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou 2003
An efficient design-for-verification technique for HDLs Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou 2001
A new method for constructing IP level power model based on power sensitivity Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou 2000
Hierarchical Floorplan Design on the Internet Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang 1999
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei 1997
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A power driven two-level logic optimizer
Jyh-Mou Tseng, Jing-Yang Jou 1997