Author: Kunihiro Asada    
Paper Titile Authors Year
CMOS-on-quartz pulse generator for low power applications Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada 2017
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada 2017
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada 2013
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada 2011
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada 2011
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada 2011
Cascaded time difference amplifier using differential logic delay cell Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada 2010
Circuit design using stripe-shaped PMELA TFTs on glass Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada 2009
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada 2007
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada 2004
Design of real-time VGA 3-D image sensor using mixed-signal techniques Yusuke Oike, Makoto Ikeda, Kunihiro Asada 2004
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada 2002
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories Tohru Ishihara, Kunihiro Asada 2002
A system level memory power optimization technique using multiple supply and threshold voltages Tohru Ishihara, Kunihiro Asada 2001
A smart position sensor for 3-D measurement Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada 2001
Finding an optimal functional decomposition for LUT-based FPGA synthesis Jian Qiao, Makoto Ikeda, Kunihiro Asada 2001
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada 2001
A binary image sensor with flexible motion vector detection using block matching method Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada 2000
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada 1998
An Analysis on VLSI Interconnection Considering Skin Effect Tetsuhisa Mido, Kunihiro Asada 1998
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Crosstalk noise in high density and high speed interconnections due to inductive coupling
Tetsuhisa Mido, Kunihiro Asada 1997