Author: Lei He    
Paper Titile Authors Year
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He 2015
A fast and provably bounded failure analysis of memory circuits in high dimensions Wei Wu, Fang Gong, GengSheng Chen, Lei He 2014
On confidence in characterization and application of variation models Lerong Cheng, Puneet Gupta, Lei He 2010
Fault-tolerant resynthesis with dual-output LUTs Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li 2010
Accounting for non-linear dependence using function driven component analysis Lerong Cheng, Puneet Gupta, Lei He 2009
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He 2009
Incremental and on-demand random walk for iterative power distribution network analysis Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He 2009
Non-Gaussian statistical timing analysis using second-order polynomial fitting Lerong Cheng, Jinjun Xiong, Lei He 2008
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong 2007
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong 2006
Constraint driven I/O planning and placement for chip-package co-design Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He 2006
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He 2005
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction Yan Lin, Fei Li, Lei He 2005
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He 2005
Probabilistic congestion model considering shielding for crosstalk reduction Jinjun Xiong, Lei He 2005
A wideband hierarchical circuit reduction for massively coupled interconnects Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan 2005
High-level area and power-up current estimation considering rich cell library Fei Li, Lei He, Joseph M Basile, Rakesh J Patel, Hema Ramamurthy 2004
Modeling of coplanar waveguide for buffered clock tree Jun Chen, Lei He 2004
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects Jun Chen, Lei He 2003
Estimation of Maximum Power-Up Current Fei Li, Lei He, Kewal K. Saluja 2002
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An efficient analytical model of coupled on-chip RLC interconnects
Liang Yin, Lei He 2001