Author: C.-J. Richard Shi    
Paper Titile Authors Year
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi 2019
Symmetry-aware placement with transitive closure graphs for analog layout design Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang 2008
A Graph Reduction Approach to Symbolic Circuit Analysis Guoyong Shi, Weiwei Chen, C.-J. Richard Shi 2007
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings Zhao Li, C.-J. Richard Shi 2006
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi 2006
An FPGA implementation of low-density parity-check code decoder with multi-rate capability Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi 2005
Hierarchical extraction and verification of symmetry constraints for analog layout automation Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi 2004
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi 2004
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi 2004
Parametric reduced order modeling for interconnect analysis Guoyong Shi, C.-J. Richard Shi 2004
Efficient DDD-based term generation algorithm for analog circuit behavioral modeling Sheldon X.-D. Tan, C.-J. Richard Shi 2003
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis Tao Pi, C.-J. Richard Shi 2000
Symbolic circuit-noise analysis and modeling with determinant decision diagrams Xiang-Dong Tan, C.-J. Richard Shi 2000
Symmetry Detection for Automatic Analog-Layout Recycling Youcef Bourai, C.-J. Richard Shi 1999
Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis Xiang-Dong Tan, C.-J. Richard Shi 1999
Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial) C.-J. Richard Shi 1998
Automatic Test Generation for Linear Analog Circuits under Parameter Variations C.-J. Richard Shi, Michael W. Tian 1998
Block-level fault isolation using partition theory and logic minimization techniques C.-J. Richard Shi 1997
Solving constrained via minimization by compact linear programming C.-J. Richard Shi 1997
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems C.-J. Richard Shi, Janusz A. Brzozowski 1995