Author: Sheqin Dong    
Paper Titile Authors Year
Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow Fengxian Jiao, Sheqin Dong 2016
Power optimization for application-specific 3D network-on-chip with multiple supply voltages Kan Wang, Sheqin Dong 2013
Linear optimal one-sided single-detour algorithm for untangling twisted bus Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto 2012
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong 2011
Network flow-based simultaneous retiming and slack budgeting for low power design Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto 2011
Floorplanning and topology generation for application-specific network-on-chip Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto 2010
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong 2008
Symmetry constraint based on mismatch analysis for analog layout in SOI technology Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto 2008
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong 2007
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 2007
Signal-path driven partition and placement for analog circuit Di Long, Xianlong Hong, Sheqin Dong 2006
An improved P-admissible floorplan representation based on Corner Block List Renshen Wang, Sheqin Dong, Xianlong Hong 2005
LFF algorithm for heterogeneous FPGA floorplanning Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu 2005
A buffer planning algorithm with congestion optimization Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
Buffer allocation algorithm with consideration of routing congestion Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu 2004
A buffer planning algorithm based on dead space redistribution Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu 2003
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu 2003
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2002
VLSI block placement using less flexibility first principles Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu 2001
VLSI floorplanning with boundary constraints based on corner block list
Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu 2001